In the field of memories generally and E.sup.2 PROMs in particular there is constant demand for shrinking geometries, increasing densities and hence reducing die. costs. However, because E.sup.2 PROM involves high voltages, certain physical breakdown effects limit the scaling of the E.sup.2 PROM cell so it cannot be shrunk as per standard 5 V logic gates.
Conventionally, E.sup.2 PROM memory cells have stored binary values, i.e. either a `0` or a `1`. In efforts to increase storage density, two schemes have been proposed for multilevel cell systems:
Firstly it has been proposed to use a large double-polysilicon cell with a number of different sized control gates, allowing the programming of multi-level values into the cell by varying the coupling capacitance ratio of the cell. However, this multi-level scheme has the drawback that it requires a very large cell, hence producing no overall density benefits.
Secondly it has been proposed to program different values into a standard Flash EEPROM cell using a number of short programming bursts, the number of bursts controlling the threshold voltage of the cell, i.e. the value to be programmed; a complex multi-reference-level comparator must be used as a sense amplifier. However, this multi-level scheme has the drawback that, although the cell itself may be small, it requires a complex sense amplifier scheme with many accurate voltage levels being necessary.